The present invention relates to a real time address switching circuit, more particularly to an address signal generation system and circuit for adding the address signal to a DRAM when DRAM multiple-bits parallel test is carried out on the basis of a 4 MDRAM multiple-bits parallel test system adopted by JEDEC (Joint Electron Device Engineering Council) held on April, 1987.
The system adopted by JEDEC is disclosed in the magazine entitled "NIKKEI MICRODEVICES" Separate Volume No. 1, published on May of 1987.
For performing the 4 MDRAM multiple-bits paralell test system (.times.4, .times.8, .times.16 parallel bits) adopted by JEDEC, it is necesary to automatically switch to the multiple-bits parallel test mode and automatically control addresses to be added to a DRAM under test on the basis of the mutiple-bits parallel test mode. The number of the data bits at the multiple-bits parallel test mode operation increases 2.sup.n as many as that at the time of normal mode operation.
It is necessary to reduce the device address to 1/2.sup.n in response to the change of the number of the data bits.